FIG. 4 illustrates the configuration of a conventional oscillation circuit, and FIG. 5 is a timing chart showing the operation of the same.
Referring to FIG. 4, an oscillation circuit 1a is provided in a microcomputer 3 and is connected through external terminals 5 to an external oscillator 7 (crystal, ceramic or the like) provided external to the microcomputer 3. In combination with the external oscillator 7 and capacitors. 19, the oscillation circuit 1a constitutes an oscillation device 9 which generates an internal clock 13 from an external clock 11 supplied by the external oscillator 7, and supplies it to the circuits in the microcomputer 3. The oscillation circuit 1a includes a two-input NAND circuit 15 and a resistor 17. The resistor 17 is connected between a first input terminal of the two-input NAND circuit 15 and an output terminal of the same. Additionally, the external oscillator 7 is also parallel-connected through the external terminals 5 as described above. Furthermore, both terminals of the external oscillator 7 are grounded through capacitors 19. The oscillation circuit 1a receives an enable signal 21 at a second input terminal of the two-input NAND circuit 15 to cause the external oscillator 7 to begin oscillating when the enable signal 21 is at a "High (H)" level and to cause the external oscillator 7 to stop oscillating when the enable signal 21 is at a "Low (L)" level.
The operation of the oscillation circuit 1a having such a configuration will be described with reference to the timing chart shown in FIG. 5. In the period between time t.sub.0 and t.sub.1, an enable signal 21 at the "L" level is output to the second input terminal of the two-input NAND circuit 15 from a CPU (central processing unit which is not shown). Therefore, the output of the two-input NAND circuit 15 always stays at the "H" level during this period regardless of the input to the first input terminal. The external oscillator 7 stops oscillating during this period as described above and therefore the internal clock 13 is not generated. At time t.sub.1 and thereafter, an enable signal 21 at the "H" level is output to the second input terminal of the two-input NAND circuit 15 from the CPU. As a result, the output terminal of the two-input NAND circuit 15 outputs a clock signal 23 which is a phase-inverted version of the external clock signal 11 input to the first input terminal. The clock signal 23 output by the oscillation circuit 1a is input to an inverter 25 to be output therefrom as the internal clock 13.
As shown in FIG. 4, the internal clock signal 13 output by the inverter circuit 25 is supplied to an internal circuit (not shown) through an oscillation stabilizer circuit 31 constituted by a counter 27 and a two-input AND circuit 29. As shown in FIG. 6, V.sub.CC (power supply voltage) does not rise to a predetermined voltage (e.g., 5 volts) immediately after the power supply is turned on. The external clock 11 (internal clock 13) is therefore stabilized only when a predetermined period of time (the period indicated by T in FIG. 6) has passed and, if such an unstable clock is supplied to the internal circuit, malfunction and errors can occur in the circuit. Therefore, the internal clock 13 is input to the counter 27 which causes an oscillation stabilization detection signal 33 to change from the "L" level to the "H" level (at the point in time indicated by t.sub.10 in FIG. 6) after counting a predetermined number of clock pulses. As the oscillation stabilization detection signal 33 input to one of the input terminals of the two-input AND circuit 29 achieves the "H" level, the circuit 29 outputs the internal clock 13 input to the other input terminal to supply it to the internal circuit. Thus, the internal clock 13 is supplied to the internal circuit only after being stabilized by the oscillation stabilizer circuit 31.
As described above, the conventional oscillation circuit generates an internal clock from an external clock supplied by an external oscillator and supplies it to an internal circuit. However, the internal circuit is not always required to operate at high speed according to a clock at a high frequency inherent in an external oscillator, for example, in a standby mode. In other words, it may be sufficient for it to operate at a low speed according to the clock at a frequency lower than the inherent frequency of the external oscillator. In such a case, it is very much more advantageous to reduce the current consumed to supply a clock at a minimum required frequency to the internal circuit. For this reason, it is a common practice to reduce the frequency of the clock supplied to an internal circuit for the purpose of reducing the current consumption, and a frequency divider circuit is normally used in such a case. A frequency divider circuit generates a clock at a frequency that is a sub-multiple of the frequency of an internal clock as described, and supplies it to an internal circuit.
However, substantially no reduction of current consumption is achieved in the entire circuit as a whole even when the internal circuit is operated at a low speed according to a low frequency clock obtained by the frequency dividing by the frequency divider circuit in an attempt to reduce the current consumed since the oscillation device itself still uses a clock at a high frequency by operating the external oscillator. This is because the oscillation device typically consumes a current higher than that consumed in the internal circuit, which amounts to a minimal reduction of the current consumed by the entire circuit when the internal circuit operates at a low speed.
The present invention has been conceived taking the above-described situation into consideration, and it is an object of the present invention to provide an oscillation circuit in which a reduction in current consumption can be achieved by stopping the oscillation of an external oscillator when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. It is another object of the present invention to provide an oscillation circuit in which a clock can be supplied to a microcomputer even when the oscillation of an external oscillator is stopped to prevent malfunction of the microcomputer due to noise from the external oscillator and to eliminate a need for adjusting the external oscillator for stable oscillation.